1. Field of the Invention
The invention relates to substrates for pre-soldering materials and fabrication methods thereof, and more particularly, to a substrate having exposed conductive pads thereon for use with a pre-soldering material applied by electroplating or stencil printing process and a fabrication method of the substrate.
2. Description of the Related Art
In the early 60, IBM has introduced a flip chip package technology characterized by having solder bumps to connect the semiconductor chip and the substrate, instead of having the gold wire as in the typical wire bonding technique. The flip chip package technology has benefits in terms of increasing package integration, and reducing package device size, while a long metal wire is not required in the flip chip package technology in order to enhance electrical function of the device. For many years, manufacturers have adopted a thermal soldering on the ceramic substrate in a technology known as control-collapse chip connection (C4). Recently, the demand for the semiconductor device of high density, high speed, and low cost is increased, the flip-chip device is mounted on a low-cost organic circuit board (such as printed circuit board (PCB) or substrate) to meet the trend for gradually minimizing the size of the electrical product. Then, the underfill resin is filled underneath the chip to reduce the thermal stress generated due to a difference in thermal expansion between the silicon chip and the organic circuit board.
In the current flip chip package technology, a plurality of conductive electrode pads are disposed on the integrated circuit (IC) chip, while corresponding conductive pads are disposed on the organic circuit board, such that the soldering bumps or other conductive adhesive materials are suitably disposed between the chip and the circuit board. The chip is mounted by electrical contacts on the circuit board in a face-down manner, wherein the soldering bumps or the conductive adhesive materials provide conductive input/output and mechanical connection between the chip and the circuit board.
Referring to FIGS. 1A and 1B, a conventional flip-chip device is proposed. As shown in the diagram, a plurality of metal bumps 11 are formed on electrode pads 12 of the chip 13, and a plurality of pre-soldering bumps 14 made of soldering material are formed on the conductive pads 15 of the organic circuit board 16. At a re-flow soldering temperature sufficient to melt the pre-soldering material, the pre-soldering bumps 14 are re-flow soldered to corresponding metal bumps to form soldering connections 17. For the solder bump joint, a gap between the chip and the circuit board is further filled with an underfill material 18 to eliminate thermal expansion difference between the chip 13 and the circuit board 16 and the stress of the soldering connections 17.
FIG. 2 illustrates a conventional organic circuit board 2 used in the flip-chip package, wherein the circuit board 2 has conductive pads 21. The insulating layer 22 of the organic circuit board 2 is made of organic material, mix fiber organic material, or mix grain organic material (compound materials such as epoxy, polyimide, bismeleimide triazine, cyanate ester, polybenzocyclobutane or their glass fibers). The conductive pads 21 are typically made of metallic material (such as copper). The common metal barrier layer 23 includes a nickel adhesive layer formed on the conductive pads 21 and a gold (Au) insulating layer formed on the nickel adhesive layer. The barrier layer 23 also includes gold (Au), nickel (Ni), palladium (Pd), silver (Ag), tin (Sn), Ni/Pd, chromium (Cr)/titanium (Ti), Pd/Au, or Ni/Pd/Au formed by electroplating, electroless plating, or physical vapor deposition. Next, an organic insulating layer 24, such as a layer of green paint is coated on the surface of the circuit board 2 to protect the wire layer above the circuit board while providing an insulating property.
As shown in FIG. 2, the conductive pads 21 are exposed from the organic insulating layer 24, and pre-soldering bumps 25 are formed on the conductive pads 21 to subsequently form flip-chip soldering joints. Currently, the stencil printing process is adopted by most of current manufacturers to deposit the solder on the conductive pads 21 so as to form the pre-soldering bumps. And the molding plate material most commonly seen in the stencil printing is a steel plate.
However, as the current development for telecommunication, network, computer, and a variety of portable products grows significantly in the actual operation, packages that enable minimization of IC area and characterized by having high density and multiple leads, such as ball grid array (BGA) package, flip chip package, chip scale package (CSP), and multi chip module (MCM) have gradually become main trend in the package market. And these packages often cooperate with the microprocessor, chip module, graphic chip, ASIC, and other highly efficient chips to achieve higher operation speed. However, as it is necessary to scale down the wire width and conductive pad, a part of area of the conductive pad 21 may be covered by the insulating layer 24 that is present between the conductive pads 21 as the pitch of the conductive pad 26 is constantly reduced, making the conductive pads 21 exposed from the insulating layer 24 even smaller. This causes misalignment for the pre-soldering bumps formed subsequently, while size of the opening in the molding plate is minimized in the stencil printing technique as a result of the space occupied by the insulating layer 24 and the height thereof. As it is not easy to mold the molding plate, the cost for fabricating the molding plate is increased. Furthermore, it is very difficult for the pre-soldering material to penetrate through the openings with the very small pitches in the molding plate. Thus, this results a bottleneck for the fabrication process.
The insulating layer 24 that covers a part of the area of the conductive pad 21 occupies space and is formed with a height, leading to an increase in amount of pre-soldering material being used as well as an increase in corresponding thickness for semiconductor substrate. As a result, the fabrication cost is increased and minimization of the semiconductor device is adversely affected. And while the pre-soldering is electroplated in the opening area of the insulating layer 24, the bond joint for the pre-soldering material is poor and unable to pass the reliability test due to a limited contact area for forming the pre-soldering material on the conductive pads.
Therefore, the above-mentioned problems associated with the prior arts are resolved by providing a substrate formed with pre-soldering material to improve problems, such as misalignment for pre-soldering material, poor bond joint, and low yield of stencil printing technique.